1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and more particularly relates to a semiconductor integrated circuit in which the phase of a circuit is adjusted by the phase adjusting function of a PLL circuit.
2. Description of the Related Art
A circuit in which a PLL circuit is controlled by a register is disclosed in Japanese Laid-Open Patent Application (JP-A-Heisei 3-205920). FIG. 1 shows the structure of such a conventional circuit.
Referring to FIG. 1, a phase synchronizing circuit is composed of a PLL circuit and a register 507. In this case, the PLL circuit is composed of a phase comparator 502, a charge pump 503, a filter 504, and a VCO 505 (voltage controlled oscillator). The phase comparator 502 compares the frequency and phase of a code data 1 501 with a feedback signal. The charge pump 503 outputs a constant current for a time period corresponding to the phase difference obtained as the comparing result by the phase comparator 502. The filter 504 converts the current output from the charge pump 503 into a corresponding voltage. The VCO 505 generates a clock signal Sync Clock 506 with the frequency corresponding to the voltage outputted from the filter 504. The register 507 stores information of a gain quantity and a filter constant and the like for the respective circuits of the PLL circuit.
In this reference, at least one of the gain of the charge pump 503, the constant of the filter 504, and the central frequency of the voltage controlled oscillator 505 is changed.
The phase synchronizing circuit is further composed of a micro-computer bus 508 for writing data in the register 507, a CPU 509 for computing the whole data, a HDC (hard disc controller) 510 in which a program for controlling the whole system is stored, and a RAM or a ROM 511. In the RAM or the ROM 511, data such as the program for the CPU 509 and the most appropriate setting values are stored.
In the phase synchronizing circuit, the CPU 509 selects setting values for the PLL circuit from the data stored in the RAM or the ROM 511. Then, the CPU 509 writes the selected values in the register 507 through the micro-computer bus 508 such that the values are sent to each of the circuits of the PLL circuit. The PLL circuit changes the gain of the charge pump, the filter constant, and/or the central frequency of the VCO.
In the above-mentioned technique, in case of use of the phase adjusting function of the PLL circuit, the output of the PLL circuit is connected with a delay element group as an input signal. The delay element group delays the output of the PLL circuit by a delay quantity determined by the delay element group to generate a phase adjusting signal. The phase synchronizing circuit adjusts the difference in phase between the input signal and the phase adjusting signal.
However there is a problem in that the delay quantity can not be changed after a LSI including the phases synchronizing circuit is manufactured and mounted on a printed circuit board.
When another LSI is connected with the phase synchronizing circuit to use one common clock signal, the other LSI does not operate normally because the phase adjustment time of the phase synchronizing circuit is fixed.